| 논문 및 저서 |
| “Self-Timed Pulsed Latch for Low Voltage Operation with 77% Hold Time Reduction," IEEE Journal of Solid-State Circuits, Vol. 54, No. 8, Pages 2304-2315 |
| “Bitline Charge-Recycling SRAM Write Assist Circuitry for Improvement and Energy Saving," IEEE Journal of Solid-State Circuits, Vol. 54, Issue. 3, Pages 896-906 |
| "Sense Amplifier-Based Flip Flop with Transition Completion Detection for Low Voltage Operation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, No. 4, Pages 609-620 |
| "Bit-line Precharging and Preamplifying Switching PMOS for High-Speed Low-Power SRAM," IEEE Transactions on Circuits and Systems II, Vol. 63, No. 11, Pages 1059-1063 |
| "Trip-point Bit-line Precharge Sensing Scheme for Singleended SRAM" IEEE Transactions on Very Large Scale Integration Systems, Vol. 23, No. 7, Pages 1370-1374 |
